New DRAM Scrambling Attack Exposes CPU Protected Memory

Key Takeaways

• A novel attack, “DRAM Scrambling,” bypasses hardware-level memory protections in modern CPUs.
• The exploit manipulates the DRAM controller’s address translation logic, effectively remapping physical memory.
• This technique affects critical security features like System Management Mode, Platform Security Processor, and even CPU microcode.
• The vulnerability is architectural, not a single patchable flaw, impacting designs from AMD, Intel, ARM, and RISC-V.

A sophisticated new attack technique has emerged, capable of circumventing some of the most robust hardware security mechanisms embedded in contemporary processors. This method targets the fundamental process of memory address translation, allowing an attacker to bypass protections surrounding System Management Mode (SMM), the Platform Security Processor (PSP), and even CPU microcode.

Security researcher Christopher Domas unveiled this innovative attack through an open-source project named skitter-creek-bath-salts on GitHub. The research illuminates a critical vulnerability residing in a layer beneath nearly all existing defense mechanisms: the address-translation logic of the DRAM controller.

Every physical address generated by a CPU must pass through this controller, which then remaps it into specific raw memory coordinates—identifying a particular bank, rank, row, and column within a DIMM module.

Crucially, robust security features such as SEV, SGX, TDX, TrustZone, and firmware-based memory carveouts all depend on the assumption that physical addresses remain constant and predictable once they leave the CPU core. Domas’s technique demonstrates that this fundamental assumption can be shattered with a single instruction.

DRAM Scrambling Attack

How the Attack Works

By manipulating specific configuration bits within the memory controller, an attacker can fundamentally alter how physical addresses map to actual DRAM cells. The research describes this process as “spaghettifying” memory. Once this remapping is modified, an entirely different address can be made to point to the exact same physical memory cell that was previously isolated and inaccessible.

Since all access-control mechanisms operating above the memory controller validate physical addresses rather than the underlying DRAM coordinates, these protections remain oblivious when the foundational memory map is altered.

This class of vulnerability is not attributable to a singular flaw that can be simply patched. The research explains that the attack is feasible because the address transform performed by the memory controller is a linear operation over GF(2). This means it can be mathematically reconstructed using basic linear algebra, often with the assistance of an SMT solver like Z3, even when the precise remapping details are not documented by the manufacturer.

Demonstrated Capabilities

Domas successfully demonstrated this technique on AMD Family 16h processors. He managed to extract the fTPM’s RSA signing routine directly from Platform Security Processor memory, a region designed to be completely isolated from the operating system.

Using the same methodology, the researcher pulled the System Management Mode (SMM) interrupt handler out of SMRAM, a memory region advertised as “locked” by the chipset. Furthermore, the attack recovered raw CPU register states, including page-table roots and APIC configuration, which are temporarily stored in DRAM while CPU cores enter the C6 low-power idle state.

Perhaps most significantly, the research reveals that a CPU’s active microcode patch, typically volatile and inaccessible, is temporarily written to DRAM during idle transitions. This allows it to be both read and overwritten using the same memory aliasing trick.

While the proof-of-concept published on GitHub targets an older AMD platform—whose datasheets coincidentally provided enough information about the controller’s registers to reverse-engineer the transform—Domas emphasizes that the underlying architectural pattern (channel and rank interleaving, bank swizzling, and chip-select mapping) is prevalent across virtually every modern memory controller design, encompassing AMD, Intel, ARM, and RISC-V architectures.

These groundbreaking findings are slated for a detailed presentation at Black Hat 2026. Researchers and the cybersecurity community are expected to closely monitor how chipmakers will address this new class of vulnerability, which fundamentally challenges the efficacy of traditional CPU security models.

What You Should Do

• Organizations should monitor for official advisories and potential microcode updates from CPU manufacturers (AMD, Intel, ARM, RISC-V) as more details emerge.
• While direct mitigation by end-users is limited for architectural vulnerabilities, maintaining strict software security practices, including timely patching of operating systems and applications, remains crucial to prevent initial compromise that could lead to exploitation of such low-level vulnerabilities.
• Security teams should stay informed about the ongoing research and discussions around “DRAM Scrambling” and similar hardware-level attacks.
• Consider advanced endpoint detection and response (EDR) solutions that may offer some visibility into unusual memory access patterns, although this attack operates at a very low level.

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